Relay Protection Academy Module 07 of 25
Module 07 Intermediate

Relay Technology
Evolution

⌛ ~2 hours 📚 IEC 60255 / IEEE C37.90 📑 12 slides

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Module 07 / 7.1

Four Generations of Relay Technology

GenerationMechanismStrengthsLimitations
Electromechanical Coils, induction discs, armatures Robust contacts, no external power, field-proven Slow, single-function, no self-monitoring
Static Transistors, thyristors, op-amps Faster, smaller, lower burden ESD sensitive, analogue drift with age
Digital 8/16-bit microprocessor, early ADC Software-settable, multiple functions 12-24 samples/cycle, limited speed
Numerical DSP, 24-80+ samples/cycle, FPGA DFT phasors, disturbance records, IEC 61850 Firmware version control required
Coexistence in service Most substations mix generations. Understanding each type's limitations is essential when designing back-up protection.

Module 07 / 7.2

Electromechanical Relays

Attracted Armature
Electromagnet attracts a hinged armature above pickup threshold. Contacts are robust - able to make and break highly inductive circuits. Still used as trip/lockout relays in numerical substations.
Induction Disc
Disc rotates between two phase-displaced electromagnets. Speed proportional to current - implements IDMT characteristic mechanically. Widely used for OC protection before digital era.
Shading loop AC flux passes through zero twice per cycle, causing chatter. A copper shading loop creates a lagging flux that is non-zero when the main flux is zero, ensuring continuous attraction.
Why they survive Numerical relay output contacts are small logic signals. Heavy-duty attracted armature relays interface these to the CB trip coil current.

Module 07 / 7.3

Static and Digital Relays

Static
  • Transistors, diodes, op-amps - no moving parts
  • ESD sensitive - always use wrist strap when handling
  • Analogue components drift with temperature and age
Digital
  • Software-settable - no potentiometers or plug bridges
  • 12-24 samples/cycle; multiple functions per unit
  • Early event logging - no waveform records
ESD hazard Opening a static relay without ESD precautions can destroy CMOS gates with no immediate visible symptom. Latent damage causes failure months later in service.
Independent DC supply Drawing auxiliary power from CT/VT quantities adds burden and creates a minimum operating threshold. Always use an independent DC supply.

Module 07 / 7.4

Numerical Relay Architecture

  1. Isolating transformers: galvanic isolation, remove transients
  2. Amplitude limiters: clamp signal within ADC range
  3. Multiplexer + ADC: time-shared conversion; timing correction needed for inter-channel accuracy
  4. DSP: DFT and protection algorithms at 24-80 samples/cycle
  5. Opto-isolated inputs: binary status from switchgear
  6. Output contacts: high-current attracted armature relays
⎓
Diagram needed

Numerical relay block diagram left to right: CT/VT inputs, isolating transformers, amplitude limiters, MUX+ADC, DSP, CPU+RAM, comms (Ethernet/RS485), opto inputs, output contacts. Dark background, labelled arrows.

Module 07 / 7.5

Nyquist and Anti-Aliasing

Nyquist criterion
Sampling rate must be at least twice the highest frequency of interest.
  • Hardware low-pass filter must attenuate all frequencies above before ADC
  • No digital processing can recover an aliased signal after conversion
⎓
Diagram needed

Aliasing diagram: high-frequency solid-line sinusoid with sparse sample points. Dashed low-frequency sinusoid through the same samples. Label: actual signal, sample points, aliased signal. Dark background.

Clipping = false harmonics Input exceeding ADC range clips the waveform. A clipped sinusoid is rich in odd harmonics - these corrupt the DFT and can cause misoperation.

Module 07 / 7.6

DFT Phasor Estimation

DFT fundamentals ( samples/cycle)
Magnitude , angle
Sampling rate
24 samples/cycle: one DFT per cycle (20 ms). 80 samples/cycle: sub-cycle updates possible for high-speed protection.
Inter-channel timing
Multiplexed ADC samples channels at slightly different instants. DSP applies phase correction per channel.
Frequency tracking
System frequency is not exactly 50/60 Hz. Relays track zero crossings and adjust the window - without this, spectral leakage corrupts measurements.

Module 07 / 7.7

VT/CT Supervision

Loss of all 3 VT phases
All voltages drop with no current change: VT failure flag. A real three-phase fault always causes a current change.
Single-phase VT loss
One VT phase lost, other two healthy, no zero-sequence current: VT fuse failure, not earth fault.
Level detector needed
Closing onto a dead-but-healthy line produces inrush current without a fault. A level detector prevents the supervision logic from misidentifying this as a fault change.
CT supervision
Unexpected zero/negative-sequence current without voltage disturbance suggests CT circuit failure. Differential schemes detect imbalance as a broken CT lead.
No VT supervision = false trip A blown VT fuse appears as an in-zone impedance to a distance relay. Without supervision, the relay issues a false Zone 1 trip.

Module 07 / 7.8

Setting Groups

Normal vs emergency generation
Grid feed has high fault current; local generation has low fault current. Pre-stored emergency group restores correct grading instantly.
Seasonal switching
Winter topology with extra transformers changes impedances. Pre-stored summer/winter groups avoid relay outages for resetting.
Maintenance outage
Parallel feeder out: remaining feeder carries doubled load. Higher OC pick-up in maintenance group prevents nuisance tripping.
Firmware version control
A firmware update changes algorithm coefficients. Record relay firmware version with every settings download - this is a safety requirement.
Switching method SCADA command, binary input, programmable logic, or front panel. Only one group is active at any time.

Module 07 / 7.9

Disturbance Recording and Time Sync

  • Relay buffers last N cycles; saves record on protection operation or input change
  • COMTRADE (IEEE C37.111): vendor-neutral .cfg + .dat format
  • Records from different substations can be compared in common tools
Fault location Time-stamp offsets between two-end records cross-correlate to give fault position - only works if both clocks are synced within one sample interval.
IRIG-B
Time code over coax or fibre. Microsecond accuracy.
IEEE 1588 PTP
Precision Time Protocol over Ethernet. Sub-microsecond; IEC 61850 compatible.
GPS 1PPS
Direct pulse-per-second to relay real-time clock.

Module 07 / Worked Example

Nyquist: 13th Harmonic on 50 Hz

Given 50 Hz system. Highest harmonic: 13th. Relay A: 24 samples/cycle. Relay B: 80 samples/cycle.

Highest frequency of interest

Minimum sampling rate

Relay A: 24 samples/cycle

13th harmonic aliases. Insufficient.
Relay B: 80 samples/cycle

Factor-3 margin. Sufficient.

Module 07

Knowledge Check