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Side-by-side illustration: left panel shows a sinusoidal AC waveform v(t) on a time axis; right panel shows the same quantity as a phasor arrow V at angle φ on a complex plane (real and imaginary axes). An equals sign connects the two representations. Dark background, clean technical style, blue accent color.
Complex plane diagram showing phasor addition: two phasor arrows Z1 and Z2 drawn tip-to-tail, with the resultant Z1+Z2 completing the triangle. Separately shows phasor multiplication as angle addition (Z1 at 30°, Z2 at 45°, product Z1·Z2 at 75°). Dark background, labeled arrows in blue and green, clean technical style.
| Expression | Polar | Rectangular | Meaning |
|---|---|---|---|
| Identity | |||
| Rotate 120° CCW | |||
| Rotate 240° CCW | |||
| Full rotation: returns to 1 | |||
| Balanced phasors sum to zero | |||
| Purely imaginary; used in sequence networks |
Impedance triangle diagram on a complex plane: horizontal axis = R (resistance), vertical axis = X (reactance). The hypotenuse is labeled |Z| with angle θ. Separate small diagrams show a resistor symbol (in-phase V and I), inductor symbol (V leads I by 90°), and capacitor symbol (I leads V by 90°). Dark background, IEC schematic style.
Under balanced conditions the three phases are equal in magnitude and displaced 120° using the a operator:
Phasor diagram showing three balanced three-phase voltage phasors Va, Vb, Vc at 120° spacing on a complex plane. Each phasor is a different color (blue, green, yellow). Separately shows a star-connected winding diagram and a delta-connected winding diagram with labeled line and phase voltages. Dark background, clean technical style.
Two IEC-style circuit diagrams side by side: left shows KVL with voltage source and three impedances in a loop, arrows showing voltage polarities summing to zero; right shows KCL at a node with four branch currents labeled I1–I4 with arrows, summing to zero. Dark background, clean schematic style, blue accent.
In fault analysis is the pre-fault voltage and determines fault current magnitude.
Two-step diagram showing Thévenin reduction: left panel shows a complex network with multiple sources and impedances connected to two terminals A and B; right panel shows the equivalent Thévenin circuit with a single voltage source Vth in series with impedance Zth at the same two terminals. A "simplifies to" arrow between them. IEC schematic style, dark background.
Every impedance in a power system has a physical value in ohms, but ohmic values change whenever the voltage base changes through a transformer. Per-unit (p.u.) notation eliminates this nuisance by expressing each quantity as a fraction of a chosen base.
Given: Generator G1 (66.6 MVA, 11 kV, X = 26%). Transformer T1 (75 MVA, 11/145 kV, X = 12.5%). System base: 100 MVA, 132 kV (HV side).